PCS7 IL: Sources FB1172, FB1173 H-system single plc

: 2021-04-22

: komatic

: H-system



hconnect



/ .





: SndH_AnaVal
: RcvH_AnaVal





SndH_AnaVal" RcvH_AnaValblock "BSEND" "BRCV". 32 MPI, PROFIBUS Industrial Ethernet.







 
{
Scl_ResetOptions ;
Scl_OverwriteBlocks:= 'y' ;
Scl_GenerateReferenceData := 'y' ;
Scl_S7ServerActive:= 'n' ;
Scl_CreateObjectCode:= 'y' ;
Scl_OptimizeObjectCode:= 'y' ;
Scl_MonitorArrayLimits:= 'n' ;
Scl_CreateDebugInfo := 'n' ;
Scl_SetOKFlag:= 'n' ;
Scl_SetMaximumStringLength:= '254'
}

//==========================================================================
TYPE "AnaVal"
 
STRUCT
Value : REAL ; //Value
ST : BYTE := B#16#80; //Signal Status
END_STRUCT ;
END_TYPE
//==========================================================================
TYPE "DigVal"
 
STRUCT
Value : BOOL ; //Value
ST : BYTE := B#16#80; //Signal Status
END_STRUCT ;
END_TYPE
 
//==========================================================================
 
FUNCTION_BLOCK FB11172 // "SndH_AnaVal"
 
TITLE ='Send 32 AnaVal Structs with PBK BSEND H'
AUTHOR : AdvLibIL
FAMILY : Comm
NAME : SndH_Ana
VERSION : '5.0'
 
 
VAR_INPUT
_ID1 { S7_edit := 'para' }: WORD ; //Physical Connection ID 1
R_ID1 { S7_edit := 'para' }: DWORD ; //Telegramm Connection ID 1
_ID2 { S7_edit := 'para' }: WORD ; //Physical Connection ID 2
R_ID2 { S7_edit := 'para' }: DWORD ; //Telegramm Connection ID 2
RdSysStEn { S7_visible := 'false' }: BOOL := TRUE; //RdSysSt: 1 = RdSysSt active, 0 = RdSysSt inactive
RedCPU : BOOL := TRUE; //Controller: 1 = Red. Controller, 0 = Single Controller
SndEn { S7_visible := 'false' }: BOOL := TRUE; //1= Send Continuously
CylMin : INT := 1; //Mimimum Wait Cycle
CylMax : INT := 10; //Maximum Wait Cycle
PV_In_Hys00 : REAL ; //EDC hysteresis PV_In0
PV_In_Hys01 : REAL ; //EDC hysteresis PV_In1
PV_In_Hys02 : REAL ; //EDC hysteresis PV_In2
PV_In_Hys03 : REAL ; //EDC hysteresis PV_In3
PV_In_Hys04 : REAL ; //EDC hysteresis PV_In4
PV_In_Hys05 : REAL ; //EDC hysteresis PV_In5
PV_In_Hys06 : REAL ; //EDC hysteresis PV_In6
PV_In_Hys07 : REAL ; //EDC hysteresis PV_In7
PV_In_Hys08 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In8
PV_In_Hys09 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In9
PV_In_Hys10 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In10
PV_In_Hys11 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In11
PV_In_Hys12 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In12
PV_In_Hys13 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In13
PV_In_Hys14 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In14
PV_In_Hys15 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In15
PV_In_Hys16 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In16
PV_In_Hys17 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In17
PV_In_Hys18 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In18
PV_In_Hys19 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In19
PV_In_Hys20 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In20
PV_In_Hys21 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In21
PV_In_Hys22 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In22
PV_In_Hys23 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In23
PV_In_Hys24 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In24
PV_In_Hys25 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In25
PV_In_Hys26 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In26
PV_In_Hys27 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In27
PV_In_Hys28 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In28
PV_In_Hys29 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In29
PV_In_Hys30 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In30
PV_In_Hys31 { S7_visible := 'false' }: REAL ; //EDC hysteresis PV_In31
PV_In0 : "AnaVal" ; //Input_00
PV_In1 : "AnaVal" ; //Input_01
PV_In2 : "AnaVal" ; //Input_02
PV_In3 : "AnaVal" ; //Input_03
PV_In4 : "AnaVal" ; //Input_04
PV_In5 : "AnaVal" ; //Input_05
PV_In6 : "AnaVal" ; //Input_06
PV_In7 : "AnaVal" ; //Input_07
PV_In8 { S7_visible := 'false' }: "AnaVal" ; //Input_08
PV_In9 { S7_visible := 'false' }: "AnaVal" ; //Input_09
PV_In10 { S7_visible := 'false' }: "AnaVal" ; //Input_10
PV_In11 { S7_visible := 'false' }: "AnaVal" ; //Input_11
PV_In12 { S7_visible := 'false' }: "AnaVal" ; //Input_12
PV_In13 { S7_visible := 'false' }: "AnaVal" ; //Input_13
PV_In14 { S7_visible := 'false' }: "AnaVal" ; //Input_14
PV_In15 { S7_visible := 'false' }: "AnaVal" ; //Input_15
PV_In16 { S7_visible := 'false' }: "AnaVal" ; //Input_16
PV_In17 { S7_visible := 'false' }: "AnaVal" ; //Input_17
PV_In18 { S7_visible := 'false' }: "AnaVal" ; //Input_18
PV_In19 { S7_visible := 'false' }: "AnaVal" ; //Input_19
PV_In20 { S7_visible := 'false' }: "AnaVal" ; //Input_20
PV_In21 { S7_visible := 'false' }: "AnaVal" ; //Input_21
PV_In22 { S7_visible := 'false' }: "AnaVal" ; //Input_22
PV_In23 { S7_visible := 'false' }: "AnaVal" ; //Input_23
PV_In24 { S7_visible := 'false' }: "AnaVal" ; //Input_24
PV_In25 { S7_visible := 'false' }: "AnaVal" ; //Input_25
PV_In26 { S7_visible := 'false' }: "AnaVal" ; //Input_26
PV_In27 { S7_visible := 'false' }: "AnaVal" ; //Input_27
PV_In28 { S7_visible := 'false' }: "AnaVal" ; //Input_28
PV_In29 { S7_visible := 'false' }: "AnaVal" ; //Input_29
PV_In30 { S7_visible := 'false' }: "AnaVal" ; //Input_30
PV_In31 { S7_visible := 'false' }: "AnaVal" ; //Input_31
END_VAR
VAR_OUTPUT
RdSysStEnOut { S7_visible := 'false' }: BOOL ; //RdSysSt: 1 = RdSysSt active, 0 = RdSysSt inactive
RedCPUOut { S7_visible := 'false' }: BOOL ; //Controller: 1 = Red. Controller, 0 = Single Controller
Snd1Mstr { S7_visible := 'false' }: BOOL ; //1 = CPU Rack 0 is Master (Red. CPU)
Snd1Run { S7_visible := 'false' }: BOOL ; //1 = CPU Rack 0 in RUN (Red. CPU)
Snd1Act { S7_dynamic := 'true' }: BOOL ; //1= Command is Active
Snd1Done { S7_dynamic := 'true' }: BOOL ; //1= Command is Done
Snd1Err : BOOL ; //1= Command Completed with Error
Snd1Stat { S7_visible := 'false' }: WORD ; //Kind of Error
Snd2Mstr { S7_visible := 'false' }: BOOL ; //1 = CPU Rack 1 is Master (Red. CPU)
Snd2Run { S7_visible := 'false' }: BOOL ; //1 = CPU Rack 1 in RUN (Red. CPU)
Snd2Act { S7_dynamic := 'true' }: BOOL ; //1= Command is Active
Snd2Done { S7_dynamic := 'true' }: BOOL ; //1= Command is Done
Snd2Err : BOOL ; //1= Command Completed with Error
Snd2Stat { S7_visible := 'false' }: WORD ; //Kind of Error
SyncLink { S7_visible := 'false' }: BOOL ; //1 = Syncronisation possible (Red. CPU)
ERR { S7_visible := 'false' }: BOOL ; //Internal ERROR (Red. CPU)
ErrCode { S7_visible := 'false' }: WORD ; //Error CODE of RDSYSST (Red. CPU)
END_VAR
VAR
SEND : STRUCT
sRdSysStEn : BOOL ; //RdSysSt: 1 = RdSysSt active, 0 = RdSysSt inactive
sRedCPUOut : BOOL ; //Controller: 1 = Red. Controller, 0 = Single Controller
sSnd1Run : BOOL ; //1 = CPU Rack 0 in RUN (Red. CPU)
sSnd1Mstr : BOOL ; //1 = CPU Rack 0 is Master (Red. CPU)
sSnd2Run : BOOL ; //1 = CPU Rack 1 in RUN (Red. CPU)
sSnd2Mstr : BOOL ; //1 = CPU Rack 1 is Master (Red. CPU)
sSyncLink : BOOL ; //1 = Syncronisation possible (Red. CPU)
sERR : BOOL ; //Internal ERROR (Red. CPU)
sRes01 : BOOL ; //Reserve
sRes02 : BOOL ; //Reserve
sRes03 : BOOL ; //Reserve
sRes04 : BOOL ; //Reserve
sRes05 : BOOL ; //Reserve
sRes06 : BOOL ; //Reserve
sRes07 : BOOL ; //Reserve
sRes08 : BOOL ; //Reserve
PV_In00 : REAL ;
PV_In01 : REAL ;
PV_In02 : REAL ;
PV_In03 : REAL ;
PV_In04 : REAL ;
PV_In05 : REAL ;
PV_In06 : REAL ;
PV_In07 : REAL ;
PV_In08 : REAL ;
PV_In09 : REAL ;
PV_In10 : REAL ;
PV_In11 : REAL ;
PV_In12 : REAL ;
PV_In13 : REAL ;
PV_In14 : REAL ;
PV_In15 : REAL ;
PV_In16 : REAL ;
PV_In17 : REAL ;
PV_In18 : REAL ;
PV_In19 : REAL ;
PV_In20 : REAL ;
PV_In21 : REAL ;
PV_In22 : REAL ;
PV_In23 : REAL ;
PV_In24 : REAL ;
PV_In25 : REAL ;
PV_In26 : REAL ;
PV_In27 : REAL ;
PV_In28 : REAL ;
PV_In29 : REAL ;
PV_In30 : REAL ;
PV_In31 : REAL ;
PV_In_ST00 : BYTE := B#16#80;
PV_In_ST01 : BYTE := B#16#80;
PV_In_ST02 : BYTE := B#16#80;
PV_In_ST03 : BYTE := B#16#80;
PV_In_ST04 : BYTE := B#16#80;
PV_In_ST05 : BYTE := B#16#80;
PV_In_ST06 : BYTE := B#16#80;
PV_In_ST07 : BYTE := B#16#80;
PV_In_ST08 : BYTE := B#16#80;
PV_In_ST09 : BYTE := B#16#80;
PV_In_ST10 : BYTE := B#16#80;
PV_In_ST11 : BYTE := B#16#80;
PV_In_ST12 : BYTE := B#16#80;
PV_In_ST13 : BYTE := B#16#80;
PV_In_ST14 : BYTE := B#16#80;
PV_In_ST15 : BYTE := B#16#80;
PV_In_ST16 : BYTE := B#16#80;
PV_In_ST17 : BYTE := B#16#80;
PV_In_ST18 : BYTE := B#16#80;
PV_In_ST19 : BYTE := B#16#80;
PV_In_ST20 : BYTE := B#16#80;
PV_In_ST21 : BYTE := B#16#80;
PV_In_ST22 : BYTE := B#16#80;
PV_In_ST23 : BYTE := B#16#80;
PV_In_ST24 : BYTE := B#16#80;
PV_In_ST25 : BYTE := B#16#80;
PV_In_ST26 : BYTE := B#16#80;
PV_In_ST27 : BYTE := B#16#80;
PV_In_ST28 : BYTE := B#16#80;
PV_In_ST29 : BYTE := B#16#80;
PV_In_ST30 : BYTE := B#16#80;
PV_In_ST31 : BYTE := B#16#80;
END_STRUCT ;
Z_MAX : INT ; //Zwangsbertragung
Z_MIN : INT ; //bertragungsperre
REQ1 : BOOL ; //bertragungsrequest
REQ2 : BOOL ; //bertragungsrequest
DATLAE : WORD := W#16#A2;
BSEND1 : "BSEND"; //SFB 12
BSEND2 : "BSEND"; //SFB 12
iRET : INT ;
SZL_HEADER : STRUCT
LENTHDR : WORD ;
N_DR : WORD ;
END_STRUCT ;
DR : STRUCT
RedInf : WORD ; //Information about Redundancy
MwStat : WORD ; //Status Byte 1+2
HSFCInfo : WORD ; //Info SFC 90 "H_CTRL"
SamFehl : WORD ; //Reserved
Bz_CPU_0 : WORD ; //Mode for CPU(0)
Bz_CPU_1 : WORD ; //Mode for CPU(1)
Bz_CPU_2 : WORD ; //Reserved
CPU_Valid : BYTE ; //Validity of variables (Bz_CPU_0 and Bz_CPU_1)
HSync_F : BYTE ; //Status of connection quality
END_STRUCT ;
BUSY : BOOL ;
STATE : WORD ; //State WORD
STATE_bool AT STATE: ARRAY[0..15] OF BOOL;
END_VAR
VAR_TEMP
sbCOM : BOOL ;
swH0Cond : WORD ; //Condition of CPU Rack 0
swH1Cond : WORD ; //Condition of CPU Rack 1
END_VAR
BEGIN
 
swH0Cond:=W#16#0;
swH1Cond:=W#16#0;
RedCPUOut:=RedCPU;
RdSysStEnOut:=RdSysStEn;
 
IF RdSysStEnOut AND RedCPUOut THEN //A7d0//
 
iRET:=RDSYSST(REQ := RedCPUOut // IN: BOOL
,SZL_ID := W#16#71 // IN: WORD
,INDEX := W#16#0 // IN: WORD
,BUSY := BUSY // OUT: BOOL
,SZL_HEADER := SZL_HEADER // OUT: STRUCT
,DR := DR // OUT: ANY
); // INT
 
STATE:=DR.MwStat;
IF iRET<>0 THEN //A7d1//
ERR:=TRUE;
ELSIF iRET=0 THEN //A7d3//
ERR:=FALSE;
END_IF; //A7d3//

ErrCode:=INT_TO_WORD(iRET);
Snd1Mstr:=STATE_bool[4];
Snd2Mstr:=STATE_bool[5];
SyncLink:=STATE_bool[8];
swH0Cond:=DR.Bz_CPU_0;
swH1Cond:=DR.Bz_CPU_1;

IF (swH0Cond=W#16#8) OR (swH0Cond=W#16#9) THEN //A7d4//
Snd1Run:=TRUE;
ELSE //A7d4//
Snd1Run:=FALSE;
END_IF; //A7d5//

IF (swH1Cond=W#16#8) OR (swH1Cond=W#16#9) THEN //A7d6//
Snd2Run:=TRUE;
ELSE //A7d6//
Snd2Run:=FALSE;
END_IF;
ELSE //A7d0//
Snd1Mstr:=FALSE;
Snd1Run:=FALSE;
Snd2Mstr:=FALSE;
Snd2Run:=FALSE;
SyncLink:=FALSE;
END_IF; //A7d8//
 
sbCOM:=FALSE;
IF (SndEn) THEN //A7d9//
IF ((Snd1Err) AND Snd2Err) THEN //A7da//
REQ1:=NOT(REQ1);
REQ2:=NOT(REQ2);
ELSE
IF ((Snd1Done) OR Snd2Done) THEN //A7dc//
REQ1:=FALSE;
REQ2:=FALSE;
ELSE
IF ((NOT(REQ1)) OR (NOT(REQ2))) THEN //A7de//
sbCOM:=((SEND.sRdSysStEn) XOR RdSysStEn) OR sbCOM;
sbCOM:=((SEND.sRedCPUOut) XOR RedCPUOut) OR sbCOM;
sbCOM:=((SEND.sSnd1Run) XOR Snd1Run) OR sbCOM;
sbCOM:=((SEND.sSnd1Mstr) XOR Snd1Mstr) OR sbCOM;
sbCOM:=((SEND.sSnd2Run) XOR Snd2Run) OR sbCOM;
sbCOM:=((SEND.sSnd2Mstr) XOR Snd2Mstr) OR sbCOM;
sbCOM:=((SEND.sSyncLink) XOR SyncLink) OR sbCOM;
sbCOM:=((SEND.sERR) XOR ERR) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In00-PV_In0.Value)>PV_In_Hys00) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In01-PV_In1.Value)>PV_In_Hys01) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In02-PV_In2.Value)>PV_In_Hys02) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In03-PV_In3.Value)>PV_In_Hys03) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In04-PV_In4.Value)>PV_In_Hys04) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In05-PV_In5.Value)>PV_In_Hys05) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In06-PV_In6.Value)>PV_In_Hys06) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In07-PV_In7.Value)>PV_In_Hys07) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In08-PV_In8.Value)>PV_In_Hys08) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In09-PV_In9.Value)>PV_In_Hys09) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In10-PV_In10.Value)>PV_In_Hys10) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In11-PV_In11.Value)>PV_In_Hys11) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In12-PV_In12.Value)>PV_In_Hys12) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In13-PV_In13.Value)>PV_In_Hys13) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In14-PV_In14.Value)>PV_In_Hys14) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In15-PV_In15.Value)>PV_In_Hys15) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In16-PV_In16.Value)>PV_In_Hys16) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In17-PV_In17.Value)>PV_In_Hys17) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In18-PV_In18.Value)>PV_In_Hys18) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In19-PV_In19.Value)>PV_In_Hys19) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In20-PV_In20.Value)>PV_In_Hys20) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In21-PV_In21.Value)>PV_In_Hys21) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In22-PV_In22.Value)>PV_In_Hys22) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In23-PV_In23.Value)>PV_In_Hys23) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In24-PV_In24.Value)>PV_In_Hys24) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In25-PV_In25.Value)>PV_In_Hys25) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In26-PV_In26.Value)>PV_In_Hys26) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In27-PV_In27.Value)>PV_In_Hys27) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In28-PV_In28.Value)>PV_In_Hys28) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In29-PV_In29.Value)>PV_In_Hys29) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In30-PV_In30.Value)>PV_In_Hys30) OR sbCOM;
sbCOM:=(ABS(SEND.PV_In31-PV_In31.Value)>PV_In_Hys31) OR sbCOM;

IF (Z_MIN>0) THEN //A7df//
sbCOM:=FALSE;
END_IF; //A7df//

IF (sbCOM) THEN //A7e0//
Z_MIN:=CylMin;
Z_MAX:=0;
ELSE
IF (Z_MAX>CylMax) THEN //A7e1//
sbCOM:=TRUE;
Z_MAX:=0;
END_IF;
END_IF; //A7e1//

REQ1:=sbCOM;
REQ2:=sbCOM;

IF (sbCOM) THEN //A7db//
SEND.sRdSysStEn:=RdSysStEn;
SEND.sRedCPUOut:=RedCPUOut;
SEND.sSnd1Run:=Snd1Run;
SEND.sSnd1Mstr:=Snd1Mstr;
SEND.sSnd2Run:=Snd2Run;
SEND.sSnd2Mstr:=Snd2Mstr;
SEND.sSyncLink:=SyncLink;
SEND.sERR:=ERR;
SEND.PV_In00:=PV_In0.Value;
SEND.PV_In01:=PV_In1.Value;
SEND.PV_In02:=PV_In2.Value;
SEND.PV_In03:=PV_In3.Value;
SEND.PV_In04:=PV_In4.Value;
SEND.PV_In05:=PV_In5.Value;
SEND.PV_In06:=PV_In6.Value;
SEND.PV_In07:=PV_In7.Value;
SEND.PV_In08:=PV_In8.Value;
SEND.PV_In09:=PV_In9.Value;
SEND.PV_In10:=PV_In10.Value;
SEND.PV_In11:=PV_In11.Value;
SEND.PV_In12:=PV_In12.Value;
SEND.PV_In13:=PV_In13.Value;
SEND.PV_In14:=PV_In14.Value;
SEND.PV_In15:=PV_In15.Value;
SEND.PV_In16:=PV_In16.Value;
SEND.PV_In17:=PV_In17.Value;
SEND.PV_In18:=PV_In18.Value;
SEND.PV_In19:=PV_In19.Value;
SEND.PV_In20:=PV_In20.Value;
SEND.PV_In21:=PV_In21.Value;
SEND.PV_In22:=PV_In22.Value;
SEND.PV_In23:=PV_In23.Value;
SEND.PV_In24:=PV_In24.Value;
SEND.PV_In25:=PV_In25.Value;
SEND.PV_In26:=PV_In26.Value;
SEND.PV_In27:=PV_In27.Value;
SEND.PV_In28:=PV_In28.Value;
SEND.PV_In29:=PV_In29.Value;
SEND.PV_In30:=PV_In30.Value;
SEND.PV_In31:=PV_In31.Value;
SEND.PV_In_ST00:=PV_In0.ST;
SEND.PV_In_ST01:=PV_In1.ST;
SEND.PV_In_ST02:=PV_In2.ST;
SEND.PV_In_ST03:=PV_In3.ST;
SEND.PV_In_ST04:=PV_In4.ST;
SEND.PV_In_ST05:=PV_In5.ST;
SEND.PV_In_ST06:=PV_In6.ST;
SEND.PV_In_ST07:=PV_In7.ST;
SEND.PV_In_ST08:=PV_In8.ST;
SEND.PV_In_ST09:=PV_In9.ST;
SEND.PV_In_ST10:=PV_In10.ST;
SEND.PV_In_ST11:=PV_In11.ST;
SEND.PV_In_ST12:=PV_In12.ST;
SEND.PV_In_ST13:=PV_In13.ST;
SEND.PV_In_ST14:=PV_In14.ST;
SEND.PV_In_ST15:=PV_In15.ST;
SEND.PV_In_ST16:=PV_In16.ST;
SEND.PV_In_ST17:=PV_In17.ST;
SEND.PV_In_ST18:=PV_In18.ST;
SEND.PV_In_ST19:=PV_In19.ST;
SEND.PV_In_ST20:=PV_In20.ST;
SEND.PV_In_ST21:=PV_In21.ST;
SEND.PV_In_ST22:=PV_In22.ST;
SEND.PV_In_ST23:=PV_In23.ST;
SEND.PV_In_ST24:=PV_In24.ST;
SEND.PV_In_ST25:=PV_In25.ST;
SEND.PV_In_ST26:=PV_In26.ST;
SEND.PV_In_ST27:=PV_In27.ST;
SEND.PV_In_ST28:=PV_In28.ST;
SEND.PV_In_ST29:=PV_In29.ST;
SEND.PV_In_ST30:=PV_In30.ST;
SEND.PV_In_ST31:=PV_In31.ST;
Snd1Act:=TRUE;
Snd2Act:=TRUE;
END_IF;
ELSE //A7de//
REQ1:=FALSE;
REQ2:=FALSE;
END_IF;
END_IF;
END_IF; //A7db//

BSEND1(REQ := REQ1 // IN: BOOL
,R := FALSE // IN: BOOL
,ID := _ID1 // IN: WORD
,R_ID := R_ID1 // IN: DWORD
,SD_1 := SEND // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);
 
IF (BSEND1.STATUS=W#16#B) THEN //A7e4//

BSEND1(REQ := FALSE // IN: BOOL
,R := FALSE // IN: BOOL
,ID := _ID1 // IN: WORD
,R_ID := R_ID1 // IN: DWORD
,SD_1 := SEND // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);
 
REQ1:=FALSE;
END_IF; //A7e4//

Snd1Done:=BSEND1.DONE;
Snd1Err:=BSEND1.ERROR;
Snd1Stat:=BSEND1.STATUS;
 
BSEND2(REQ := REQ2 // IN: BOOL
,R := FALSE // IN: BOOL
,ID := _ID2 // IN: WORD
,R_ID := R_ID2 // IN: DWORD
,SD_1 := SEND // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);

IF (BSEND2.STATUS=W#16#B) THEN //A7e5//
 
BSEND2(REQ := FALSE // IN: BOOL
,R := FALSE // IN: BOOL
,ID := _ID2 // IN: WORD
,R_ID := R_ID2 // IN: DWORD
,SD_1 := SEND // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);

REQ2:=FALSE;
END_IF; //A7e5//

Snd2Done:=BSEND2.DONE;
Snd2Err:=BSEND2.ERROR;
Snd2Stat:=BSEND2.STATUS;

IF (Z_MIN>0) THEN //A7e6//
Z_MIN:=Z_MIN-1;
END_IF; //A7e6//
Z_MAX:=Z_MAX+1;
ELSE
IF ((REQ1) OR REQ2) THEN //A7e8//
 
BSEND1(REQ := FALSE // IN: BOOL
,R := TRUE // IN: BOOL
,ID := _ID1 // IN: WORD
,R_ID := R_ID1 // IN: DWORD
,SD_1 := SEND // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);
 
BSEND2(REQ := FALSE // IN: BOOL
,R := TRUE // IN: BOOL
,ID := _ID2 // IN: WORD
,R_ID := R_ID2 // IN: DWORD
,SD_1 := SEND // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);
 
REQ1:=FALSE;
REQ2:=FALSE;

BSEND1(REQ := TRUE // IN: BOOL
,R := TRUE // IN: BOOL
,ID := _ID1 // IN: WORD
,R_ID := R_ID1 // IN: DWORD
,SD_1 := SEND // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);

BSEND2(REQ := TRUE // IN: BOOL
,R := TRUE // IN: BOOL
,ID := _ID2 // IN: WORD
,R_ID := R_ID2 // IN: DWORD
,SD_1 := SEND // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);

BSEND1(REQ := FALSE // IN: BOOL
,R := FALSE // IN: BOOL
,ID := _ID1 // IN: WORD
,R_ID := R_ID1 // IN: DWORD
,SD_1 := SEND // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);

BSEND2(REQ := FALSE // IN: BOOL
,R := FALSE // IN: BOOL
,ID := _ID2 // IN: WORD
,R_ID := R_ID2 // IN: DWORD
,SD_1 := SEND // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);

Snd1Done:=BSEND1.DONE;
Snd1Err:=BSEND1.ERROR;
Snd1Stat:=BSEND1.STATUS;
Snd2Done:=BSEND2.DONE;
Snd2Err:=BSEND2.ERROR;
Snd2Stat:=BSEND2.STATUS;
END_IF; //A7e8//
 
Snd1Act:=FALSE;
Snd2Act:=FALSE;
Z_MIN:=0;
Z_MAX:=0;
 
END_IF; //A7e7//
 
 
END_FUNCTION_BLOCK
 
//==========================================================================
 
FUNCTION_BLOCK FB11173 // "RcvH_AnaVal"
TITLE ='Receive 32 AnaVal Structur with PBK BRCV H'
AUTHOR : AdvLibIL
FAMILY : Comm
NAME : RcvH_Ana
VERSION : '5.0'
 
 
VAR_INPUT
_ID1 { S7_edit := 'para' }: WORD ; //Physical Connection ID 1
R_ID1 { S7_edit := 'para' }: DWORD ; //Telegramm Connection ID 1
_ID2 { S7_edit := 'para' }: WORD ; //Physical Connection ID 2
R_ID2 { S7_edit := 'para' }: DWORD ; //Telegramm Connection ID 2
RcvMonCyc { S7_visible := 'false' }: INT := 3; //nuber of Cycle for Receive Monitoring Error
SimOn { S7_edit := 'para' }: STRUCT //1=Simulation active
Value : BOOL ; //Value
ST : BYTE := B#16#80; //Signal Status
END_STRUCT ;
SimPV0 { S7_edit := 'para' }: REAL ; //Simulation value
SimPV1 { S7_edit := 'para' }: REAL ; //Simulation value
SimPV2 { S7_edit := 'para' }: REAL ; //Simulation value
SimPV3 { S7_edit := 'para' }: REAL ; //Simulation value
SimPV4 { S7_edit := 'para' }: REAL ; //Simulation value
SimPV5 { S7_edit := 'para' }: REAL ; //Simulation value
SimPV6 { S7_edit := 'para' }: REAL ; //Simulation value
SimPV7 { S7_edit := 'para' }: REAL ; //Simulation value
SimPV8 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV9 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV10 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV11 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV12 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV13 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV14 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV15 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV16 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV17 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV18 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV19 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV20 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV21 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV22 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV23 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV24 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV25 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV26 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV27 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV28 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV29 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV30 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SimPV31 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Simulation value
SubsPV0 { S7_edit := 'para' }: REAL ; //Substitut value
SubsPV1 { S7_edit := 'para' }: REAL ; //Substitut value
SubsPV2 { S7_edit := 'para' }: REAL ; //Substitut value
SubsPV3 { S7_edit := 'para' }: REAL ; //Substitut value
SubsPV4 { S7_edit := 'para' }: REAL ; //Substitut value
SubsPV5 { S7_edit := 'para' }: REAL ; //Substitut value
SubsPV6 { S7_edit := 'para' }: REAL ; //Substitut value
SubsPV7 { S7_edit := 'para' }: REAL ; //Substitut value
SubsPV8 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV9 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV10 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV11 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV12 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV13 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV14 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV15 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV16 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV17 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV18 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV19 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV20 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV21 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV22 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV23 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV24 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV25 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV26 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV27 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV28 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV29 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV30 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
SubsPV31 { S7_edit := 'para'; S7_visible := 'false' }: REAL ; //Substitut value
Feature { S7_visible := 'false' }: STRUCT //Status of various features
Bit0 : BOOL ; //Reserved
Bit1 : BOOL ; //Reserved
Bit2 : BOOL ; //Reserved
Bit3 : BOOL ; //Reserved
Bit4 : BOOL ; //Reserved
Bit5 : BOOL ; //Reserved
Bit6 : BOOL ; //Reserved
Bit7 : BOOL ; //Reserved
Bit8 : BOOL ; //Reserved
Bit9 : BOOL ; //Reserved
Bit10 : BOOL ; //Reserved
Bit11 : BOOL ; //Reserved
Bit12 : BOOL ; //Reserved
Bit13 : BOOL ; //Reserved
Bit14 : BOOL ; //Reserved
Bit15 : BOOL ; //Reserved
Bit16 : BOOL ; //Reserved
Bit17 : BOOL ; //Reserved
Bit18 : BOOL ; //Reserved
Bit19 : BOOL ; //Reserved
Bit20 : BOOL ; //Reserved
Bit21 : BOOL ; //Reserved
Bit22 : BOOL ; //Reserved
Bit23 : BOOL ; //Reserved
Bit24 : BOOL ; //Reserved
Bit25 : BOOL ; //Reserved
Bit26 : BOOL ; //Reserved
Bit27 : BOOL ; //Reserved
Bit28 : BOOL ; //Reserved
Bit29 : BOOL ; //1 = Substitute value
Bit30 : BOOL ; //Reserved
Bit31 : BOOL ; //Reserved
END_STRUCT ;
END_VAR
VAR_OUTPUT
PV_Out0 : "AnaVal" ; //Output_00
PV_Out1 : "AnaVal" ; //Output_01
PV_Out2 : "AnaVal" ; //Output_02
PV_Out3 : "AnaVal" ; //Output_03
PV_Out4 : "AnaVal" ; //Output_04
PV_Out5 : "AnaVal" ; //Output_05
PV_Out6 : "AnaVal" ; //Output_06
PV_Out7 : "AnaVal" ; //Output_07
PV_Out8 { S7_visible := 'false' }: "AnaVal" ; //Output_08
PV_Out9 { S7_visible := 'false' }: "AnaVal" ; //Output_09
PV_Out10 { S7_visible := 'false' }: "AnaVal"; //Output_10
PV_Out11 { S7_visible := 'false' }: "AnaVal"; //Output_11
PV_Out12 { S7_visible := 'false' }: "AnaVal"; //Output_12
PV_Out13 { S7_visible := 'false' }: "AnaVal"; //Output_13
PV_Out14 { S7_visible := 'false' }: "AnaVal"; //Output_14
PV_Out15 { S7_visible := 'false' }: "AnaVal"; //Output_15
PV_Out16 { S7_visible := 'false' }: "AnaVal"; //Output_16
PV_Out17 { S7_visible := 'false' }: "AnaVal"; //Output_17
PV_Out18 { S7_visible := 'false' }: "AnaVal"; //Output_18
PV_Out19 { S7_visible := 'false' }: "AnaVal"; //Output_19
PV_Out20 { S7_visible := 'false' }: "AnaVal"; //Output_20
PV_Out21 { S7_visible := 'false' }: "AnaVal"; //Output_21
PV_Out22 { S7_visible := 'false' }: "AnaVal"; //Output_22
PV_Out23 { S7_visible := 'false' }: "AnaVal"; //Output_23
PV_Out24 { S7_visible := 'false' }: "AnaVal"; //Output_24
PV_Out25 { S7_visible := 'false' }: "AnaVal"; //Output_25
PV_Out26 { S7_visible := 'false' }: "AnaVal"; //Output_26
PV_Out27 { S7_visible := 'false' }: "AnaVal"; //Output_27
PV_Out28 { S7_visible := 'false' }: "AnaVal"; //Output_28
PV_Out29 { S7_visible := 'false' }: "AnaVal"; //Output_29
PV_Out30 { S7_visible := 'false' }: "AnaVal"; //Output_30
PV_Out31 { S7_visible := 'false' }: "AnaVal"; //Output_31

SimAct { S7_visible := 'false' }: "DigVal"; //1=Simulation active

RdSysStEnOut { S7_visible := 'false' }: BOOL ; //RdSysSt: 1 = RdSysSt active, 0 = RdSysSt inactive
RedCPUOut { S7_visible := 'false' }: BOOL ; //Controller: 1 = Red. Controller, 0 = Single Controller
Rcv1Mstr { S7_visible := 'false' }: BOOL ; //1 = CPU Rack 0 is Master (Red. CPU)
Rcv1Run { S7_visible := 'false' }: BOOL ; //1 = CPU Rack 0 in RUN (Red. CPU)
Rcv1MonErr { S7_dynamic := 'true' }: BOOL ; //1= No Data Received
Rcv1NewData { S7_dynamic := 'true' }: BOOL ; //1= New Data Received
Rcv1Err : BOOL ; //1= Command Completed with Error
Rcv1Stat { S7_visible := 'false' }: WORD ; //Kind of Error
Rcv2Mstr { S7_visible := 'false' }: BOOL ; //1 = CPU Rack 1 is Master (Red. CPU)
Rcv2Run { S7_visible := 'false' }: BOOL ; //1 = CPU Rack 1 in RUN (Red. CPU)
Rcv2MonErr { S7_dynamic := 'true' }: BOOL ; //1= No Data Received
Rcv2NewData { S7_dynamic := 'true' }: BOOL ; //1= New Data Received
Rcv2Err : BOOL ; //1= Command Completed with Error
Rcv2Stat { S7_visible := 'false' }: WORD ; //Kind of Error
SyncLink { S7_visible := 'false' }: BOOL ; //1 = Syncronisation possible (Red. CPU)
ERR { S7_visible := 'false' }: BOOL ; //Internal ERROR (Red. CPU)
END_VAR
VAR
DATLAE : WORD := W#16#A2;
REC1_CNT : INT ; //Empfangszhler
REC2_CNT : INT ; //Empfangszhler
REC1 : STRUCT
sRdSysStEn : BOOL ; //RdSysSt: 1 = RdSysSt active, 0 = RdSysSt inactive
sRedCPUOut : BOOL ; //Controller: 1 = Red. Controller, 0 = Single Controller
sRcv1Run : BOOL ; //1 = CPU Rack 0 in RUN (Red. CPU)
sRcv1Mstr : BOOL ; //1 = CPU Rack 0 is Master (Red. CPU)
sRcv2Run : BOOL ; //1 = CPU Rack 1 in RUN (Red. CPU)
sRcv2Mstr : BOOL ; //1 = CPU Rack 1 is Master (Red. CPU)
sSyncLink : BOOL ; //1 = Syncronisation possible (Red. CPU)
sERR : BOOL ; //Internal ERROR (Red. CPU)
sRes01 : BOOL ; //Reserve
sRes02 : BOOL ; //Reserve
sRes03 : BOOL ; //Reserve
sRes04 : BOOL ; //Reserve
sRes05 : BOOL ; //Reserve
sRes06 : BOOL ; //Reserve
sRes07 : BOOL ; //Reserve
sRes08 : BOOL ; //Reserve
PV_Out0 : REAL ;
PV_Out1 : REAL ;
PV_Out2 : REAL ;
PV_Out3 : REAL ;
PV_Out4 : REAL ;
PV_Out5 : REAL ;
PV_Out6 : REAL ;
PV_Out7 : REAL ;
PV_Out8 : REAL ;
PV_Out9 : REAL ;
PV_Out10 : REAL ;
PV_Out11 : REAL ;
PV_Out12 : REAL ;
PV_Out13 : REAL ;
PV_Out14 : REAL ;
PV_Out15 : REAL ;
PV_Out16 : REAL ;
PV_Out17 : REAL ;
PV_Out18 : REAL ;
PV_Out19 : REAL ;
PV_Out20 : REAL ;
PV_Out21 : REAL ;
PV_Out22 : REAL ;
PV_Out23 : REAL ;
PV_Out24 : REAL ;
PV_Out25 : REAL ;
PV_Out26 : REAL ;
PV_Out27 : REAL ;
PV_Out28 : REAL ;
PV_Out29 : REAL ;
PV_Out30 : REAL ;
PV_Out31 : REAL ;
PV_Out_ST0 : BYTE := B#16#80;
PV_Out_ST1 : BYTE := B#16#80;
PV_Out_ST2 : BYTE := B#16#80;
PV_Out_ST3 : BYTE := B#16#80;
PV_Out_ST4 : BYTE := B#16#80;
PV_Out_ST5 : BYTE := B#16#80;
PV_Out_ST6 : BYTE := B#16#80;
PV_Out_ST7 : BYTE := B#16#80;
PV_Out_ST8 : BYTE := B#16#80;
PV_Out_ST9 : BYTE := B#16#80;
PV_Out_ST10 : BYTE := B#16#80;
PV_Out_ST11 : BYTE := B#16#80;
PV_Out_ST12 : BYTE := B#16#80;
PV_Out_ST13 : BYTE := B#16#80;
PV_Out_ST14 : BYTE := B#16#80;
PV_Out_ST15 : BYTE := B#16#80;
PV_Out_ST16 : BYTE := B#16#80;
PV_Out_ST17 : BYTE := B#16#80;
PV_Out_ST18 : BYTE := B#16#80;
PV_Out_ST19 : BYTE := B#16#80;
PV_Out_ST20 : BYTE := B#16#80;
PV_Out_ST21 : BYTE := B#16#80;
PV_Out_ST22 : BYTE := B#16#80;
PV_Out_ST23 : BYTE := B#16#80;
PV_Out_ST24 : BYTE := B#16#80;
PV_Out_ST25 : BYTE := B#16#80;
PV_Out_ST26 : BYTE := B#16#80;
PV_Out_ST27 : BYTE := B#16#80;
PV_Out_ST28 : BYTE := B#16#80;
PV_Out_ST29 : BYTE := B#16#80;
PV_Out_ST30 : BYTE := B#16#80;
PV_Out_ST31 : BYTE := B#16#80;
END_STRUCT ;
REC2 : STRUCT
sRdSysStEn : BOOL ; //RdSysSt: 1 = RdSysSt active, 0 = RdSysSt inactive
sRedCPUOut : BOOL ; //Controller: 1 = Red. Controller, 0 = Single Controller
sRcv1Run : BOOL ; //1 = CPU Rack 0 in RUN (Red. CPU)
sRcv1Mstr : BOOL ; //1 = CPU Rack 0 is Master (Red. CPU)
sRcv2Run : BOOL ; //1 = CPU Rack 1 in RUN (Red. CPU)
sRcv2Mstr : BOOL ; //1 = CPU Rack 1 is Master (Red. CPU)
sSyncLink : BOOL ; //1 = Syncronisation possible (Red. CPU)
sERR : BOOL ; //Internal ERROR (Red. CPU)
sRes01 : BOOL ; //Reserve
sRes02 : BOOL ; //Reserve
sRes03 : BOOL ; //Reserve
sRes04 : BOOL ; //Reserve
sRes05 : BOOL ; //Reserve
sRes06 : BOOL ; //Reserve
sRes07 : BOOL ; //Reserve
sRes08 : BOOL ; //Reserve
PV_Out0 : REAL ;
PV_Out1 : REAL ;
PV_Out2 : REAL ;
PV_Out3 : REAL ;
PV_Out4 : REAL ;
PV_Out5 : REAL ;
PV_Out6 : REAL ;
PV_Out7 : REAL ;
PV_Out8 : REAL ;
PV_Out9 : REAL ;
PV_Out10 : REAL ;
PV_Out11 : REAL ;
PV_Out12 : REAL ;
PV_Out13 : REAL ;
PV_Out14 : REAL ;
PV_Out15 : REAL ;
PV_Out16 : REAL ;
PV_Out17 : REAL ;
PV_Out18 : REAL ;
PV_Out19 : REAL ;
PV_Out20 : REAL ;
PV_Out21 : REAL ;
PV_Out22 : REAL ;
PV_Out23 : REAL ;
PV_Out24 : REAL ;
PV_Out25 : REAL ;
PV_Out26 : REAL ;
PV_Out27 : REAL ;
PV_Out28 : REAL ;
PV_Out29 : REAL ;
PV_Out30 : REAL ;
PV_Out31 : REAL ;
PV_Out_ST0 : BYTE := B#16#80;
PV_Out_ST1 : BYTE := B#16#80;
PV_Out_ST2 : BYTE := B#16#80;
PV_Out_ST3 : BYTE := B#16#80;
PV_Out_ST4 : BYTE := B#16#80;
PV_Out_ST5 : BYTE := B#16#80;
PV_Out_ST6 : BYTE := B#16#80;
PV_Out_ST7 : BYTE := B#16#80;
PV_Out_ST8 : BYTE := B#16#80;
PV_Out_ST9 : BYTE := B#16#80;
PV_Out_ST10 : BYTE := B#16#80;
PV_Out_ST11 : BYTE := B#16#80;
PV_Out_ST12 : BYTE := B#16#80;
PV_Out_ST13 : BYTE := B#16#80;
PV_Out_ST14 : BYTE := B#16#80;
PV_Out_ST15 : BYTE := B#16#80;
PV_Out_ST16 : BYTE := B#16#80;
PV_Out_ST17 : BYTE := B#16#80;
PV_Out_ST18 : BYTE := B#16#80;
PV_Out_ST19 : BYTE := B#16#80;
PV_Out_ST20 : BYTE := B#16#80;
PV_Out_ST21 : BYTE := B#16#80;
PV_Out_ST22 : BYTE := B#16#80;
PV_Out_ST23 : BYTE := B#16#80;
PV_Out_ST24 : BYTE := B#16#80;
PV_Out_ST25 : BYTE := B#16#80;
PV_Out_ST26 : BYTE := B#16#80;
PV_Out_ST27 : BYTE := B#16#80;
PV_Out_ST28 : BYTE := B#16#80;
PV_Out_ST29 : BYTE := B#16#80;
PV_Out_ST30 : BYTE := B#16#80;
PV_Out_ST31 : BYTE := B#16#80;
END_STRUCT ;
BRCV1 : "BRCV"; //SFB 13
BRCV2 : "BRCV"; //SFB 13
END_VAR
VAR_TEMP
SubOn : BOOL ; //true = substitution on error active
END_VAR
BEGIN
SubOn:=Feature.Bit29;
SimAct.Value:=SimOn.Value;
IF (SimOn.Value) THEN //A7d0//
PV_Out0.Value:=SimPV0;
PV_Out0.ST:=B#16#60;
PV_Out1.Value:=SimPV1;
PV_Out1.ST:=B#16#60;
PV_Out2.Value:=SimPV2;
PV_Out2.ST:=B#16#60;
PV_Out3.Value:=SimPV3;
PV_Out3.ST:=B#16#60;
PV_Out4.Value:=SimPV4;
PV_Out4.ST:=B#16#60;
PV_Out5.Value:=SimPV5;
PV_Out5.ST:=B#16#60;
PV_Out6.Value:=SimPV6;
PV_Out6.ST:=B#16#60;
PV_Out7.Value:=SimPV7;
PV_Out7.ST:=B#16#60;
PV_Out8.Value:=SimPV8;
PV_Out8.ST:=B#16#60;
PV_Out9.Value:=SimPV9;
PV_Out9.ST:=B#16#60;
PV_Out10.Value:=SimPV10;
PV_Out10.ST:=B#16#60;
PV_Out11.Value:=SimPV11;
PV_Out11.ST:=B#16#60;
PV_Out12.Value:=SimPV12;
PV_Out12.ST:=B#16#60;
PV_Out13.Value:=SimPV13;
PV_Out13.ST:=B#16#60;
PV_Out14.Value:=SimPV14;
PV_Out14.ST:=B#16#60;
PV_Out15.Value:=SimPV15;
PV_Out15.ST:=B#16#60;
PV_Out16.Value:=SimPV16;
PV_Out16.ST:=B#16#60;
PV_Out17.Value:=SimPV17;
PV_Out17.ST:=B#16#60;
PV_Out18.Value:=SimPV18;
PV_Out18.ST:=B#16#60;
PV_Out19.Value:=SimPV19;
PV_Out19.ST:=B#16#60;
PV_Out20.Value:=SimPV20;
PV_Out20.ST:=B#16#60;
PV_Out21.Value:=SimPV21;
PV_Out21.ST:=B#16#60;
PV_Out22.Value:=SimPV22;
PV_Out22.ST:=B#16#60;
PV_Out23.Value:=SimPV23;
PV_Out23.ST:=B#16#60;
PV_Out24.Value:=SimPV24;
PV_Out24.ST:=B#16#60;
PV_Out25.Value:=SimPV25;
PV_Out25.ST:=B#16#60;
PV_Out26.Value:=SimPV26;
PV_Out26.ST:=B#16#60;
PV_Out27.Value:=SimPV27;
PV_Out27.ST:=B#16#60;
PV_Out28.Value:=SimPV28;
PV_Out28.ST:=B#16#60;
PV_Out29.Value:=SimPV29;
PV_Out29.ST:=B#16#60;
PV_Out30.Value:=SimPV30;
PV_Out30.ST:=B#16#60;
PV_Out31.Value:=SimPV31;
PV_Out31.ST:=B#16#60;
REC1_CNT:=0;
REC2_CNT:=0;
Rcv1MonErr:=FALSE;
Rcv2MonErr:=FALSE;
ELSE //A7d0//
BRCV1(EN_R := TRUE // IN: BOOL
,ID := _ID1 // IN: WORD
,R_ID := R_ID1 // IN: DWORD
,RD_1 := REC1 // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);
 
Rcv1NewData:=BRCV1.NDR;
Rcv1Err:=BRCV1.ERROR;
Rcv1Stat:=BRCV1.STATUS;
 
BRCV2(EN_R := TRUE // IN: BOOL
,ID := _ID2 // IN: WORD
,R_ID := R_ID2 // IN: DWORD
,RD_1 := REC2 // INOUT: ANY
,LEN := DATLAE // INOUT: WORD
);
 
Rcv2NewData:=BRCV2.NDR;
Rcv2Err:=BRCV2.ERROR;
Rcv2Stat:=BRCV2.STATUS;
 
IF ((NOT(Rcv1Err)) AND Rcv1NewData) THEN //A7d2//
RdSysStEnOut:=REC1.sRdSysStEn;
RedCPUOut:=REC1.sRedCPUOut;
Rcv1Run:=REC1.sRcv1Run;
Rcv1Mstr:=REC1.sRcv1Mstr;
Rcv2Run:=REC1.sRcv2Run;
Rcv2Mstr:=REC1.sRcv2Mstr;
SyncLink:=REC1.sSyncLink;
ERR:=REC1.sERR;
PV_Out0.Value:=REC1.PV_Out0;
PV_Out1.Value:=REC1.PV_Out1;
PV_Out2.Value:=REC1.PV_Out2;
PV_Out3.Value:=REC1.PV_Out3;
PV_Out4.Value:=REC1.PV_Out4;
PV_Out5.Value:=REC1.PV_Out5;
PV_Out6.Value:=REC1.PV_Out6;
PV_Out7.Value:=REC1.PV_Out7;
PV_Out8.Value:=REC1.PV_Out8;
PV_Out9.Value:=REC1.PV_Out9;
PV_Out10.Value:=REC1.PV_Out10;
PV_Out11.Value:=REC1.PV_Out11;
PV_Out12.Value:=REC1.PV_Out12;
PV_Out13.Value:=REC1.PV_Out13;
PV_Out14.Value:=REC1.PV_Out14;
PV_Out15.Value:=REC1.PV_Out15;
PV_Out16.Value:=REC1.PV_Out16;
PV_Out17.Value:=REC1.PV_Out17;
PV_Out18.Value:=REC1.PV_Out18;
PV_Out19.Value:=REC1.PV_Out19;
PV_Out20.Value:=REC1.PV_Out20;
PV_Out21.Value:=REC1.PV_Out21;
PV_Out22.Value:=REC1.PV_Out22;
PV_Out23.Value:=REC1.PV_Out23;
PV_Out24.Value:=REC1.PV_Out24;
PV_Out25.Value:=REC1.PV_Out25;
PV_Out26.Value:=REC1.PV_Out26;
PV_Out27.Value:=REC1.PV_Out27;
PV_Out28.Value:=REC1.PV_Out28;
PV_Out29.Value:=REC1.PV_Out29;
PV_Out30.Value:=REC1.PV_Out30;
PV_Out31.Value:=REC1.PV_Out31;
PV_Out0.ST:=REC1.PV_Out_ST0;
PV_Out1.ST:=REC1.PV_Out_ST1;
PV_Out2.ST:=REC1.PV_Out_ST2;
PV_Out3.ST:=REC1.PV_Out_ST3;
PV_Out4.ST:=REC1.PV_Out_ST4;
PV_Out5.ST:=REC1.PV_Out_ST5;
PV_Out6.ST:=REC1.PV_Out_ST6;
PV_Out7.ST:=REC1.PV_Out_ST7;
PV_Out8.ST:=REC1.PV_Out_ST8;
PV_Out9.ST:=REC1.PV_Out_ST9;
PV_Out10.ST:=REC1.PV_Out_ST10;
PV_Out11.ST:=REC1.PV_Out_ST11;
PV_Out12.ST:=REC1.PV_Out_ST12;
PV_Out13.ST:=REC1.PV_Out_ST13;
PV_Out14.ST:=REC1.PV_Out_ST14;
PV_Out15.ST:=REC1.PV_Out_ST15;
PV_Out16.ST:=REC1.PV_Out_ST16;
PV_Out17.ST:=REC1.PV_Out_ST17;
PV_Out18.ST:=REC1.PV_Out_ST18;
PV_Out19.ST:=REC1.PV_Out_ST19;
PV_Out20.ST:=REC1.PV_Out_ST20;
PV_Out21.ST:=REC1.PV_Out_ST21;
PV_Out22.ST:=REC1.PV_Out_ST22;
PV_Out23.ST:=REC1.PV_Out_ST23;
PV_Out24.ST:=REC1.PV_Out_ST24;
PV_Out25.ST:=REC1.PV_Out_ST25;
PV_Out26.ST:=REC1.PV_Out_ST26;
PV_Out27.ST:=REC1.PV_Out_ST27;
PV_Out28.ST:=REC1.PV_Out_ST28;
PV_Out29.ST:=REC1.PV_Out_ST29;
PV_Out30.ST:=REC1.PV_Out_ST30;
PV_Out31.ST:=REC1.PV_Out_ST31;
REC1_CNT:=0;
Rcv1MonErr:=FALSE;
ELSIF ((NOT(Rcv2Err)) AND Rcv2NewData) THEN //A7d4//
RdSysStEnOut:=REC2.sRdSysStEn;
RedCPUOut:=REC2.sRedCPUOut;
Rcv1Run:=REC2.sRcv1Run;
Rcv1Mstr:=REC2.sRcv1Mstr;
Rcv2Run:=REC2.sRcv2Run;
Rcv2Mstr:=REC2.sRcv2Mstr;
SyncLink:=REC2.sSyncLink;
ERR:=REC2.sERR;
PV_Out0.Value:=REC2.PV_Out0;
PV_Out1.Value:=REC2.PV_Out1;
PV_Out2.Value:=REC2.PV_Out2;
PV_Out3.Value:=REC2.PV_Out3;
PV_Out4.Value:=REC2.PV_Out4;
PV_Out5.Value:=REC2.PV_Out5;
PV_Out6.Value:=REC2.PV_Out6;
PV_Out7.Value:=REC2.PV_Out7;
PV_Out8.Value:=REC2.PV_Out8;
PV_Out9.Value:=REC2.PV_Out9;
PV_Out10.Value:=REC2.PV_Out10;
PV_Out11.Value:=REC2.PV_Out11;
PV_Out12.Value:=REC2.PV_Out12;
PV_Out13.Value:=REC2.PV_Out13;
PV_Out14.Value:=REC2.PV_Out14;
PV_Out15.Value:=REC2.PV_Out15;
PV_Out16.Value:=REC2.PV_Out16;
PV_Out17.Value:=REC2.PV_Out17;
PV_Out18.Value:=REC2.PV_Out18;
PV_Out19.Value:=REC2.PV_Out19;
PV_Out20.Value:=REC2.PV_Out20;
PV_Out21.Value:=REC2.PV_Out21;
PV_Out22.Value:=REC2.PV_Out22;
PV_Out23.Value:=REC2.PV_Out23;
PV_Out24.Value:=REC2.PV_Out24;
PV_Out25.Value:=REC2.PV_Out25;
PV_Out26.Value:=REC2.PV_Out26;
PV_Out27.Value:=REC2.PV_Out27;
PV_Out28.Value:=REC2.PV_Out28;
PV_Out29.Value:=REC2.PV_Out29;
PV_Out30.Value:=REC2.PV_Out30;
PV_Out31.Value:=REC2.PV_Out31;
PV_Out0.ST:=REC2.PV_Out_ST0;
PV_Out1.ST:=REC2.PV_Out_ST1;
PV_Out2.ST:=REC2.PV_Out_ST2;
PV_Out3.ST:=REC2.PV_Out_ST3;
PV_Out4.ST:=REC2.PV_Out_ST4;
PV_Out5.ST:=REC2.PV_Out_ST5;
PV_Out6.ST:=REC2.PV_Out_ST6;
PV_Out7.ST:=REC2.PV_Out_ST7;
PV_Out8.ST:=REC2.PV_Out_ST8;
PV_Out9.ST:=REC2.PV_Out_ST9;
PV_Out10.ST:=REC2.PV_Out_ST10;
PV_Out11.ST:=REC2.PV_Out_ST11;
PV_Out12.ST:=REC2.PV_Out_ST12;
PV_Out13.ST:=REC2.PV_Out_ST13;
PV_Out14.ST:=REC2.PV_Out_ST14;
PV_Out15.ST:=REC2.PV_Out_ST15;
PV_Out16.ST:=REC2.PV_Out_ST16;
PV_Out17.ST:=REC2.PV_Out_ST17;
PV_Out18.ST:=REC2.PV_Out_ST18;
PV_Out19.ST:=REC2.PV_Out_ST19;
PV_Out20.ST:=REC2.PV_Out_ST20;
PV_Out21.ST:=REC2.PV_Out_ST21;
PV_Out22.ST:=REC2.PV_Out_ST22;
PV_Out23.ST:=REC2.PV_Out_ST23;
PV_Out24.ST:=REC2.PV_Out_ST24;
PV_Out25.ST:=REC2.PV_Out_ST25;
PV_Out26.ST:=REC2.PV_Out_ST26;
PV_Out27.ST:=REC2.PV_Out_ST27;
PV_Out28.ST:=REC2.PV_Out_ST28;
PV_Out29.ST:=REC2.PV_Out_ST29;
PV_Out30.ST:=REC2.PV_Out_ST30;
PV_Out31.ST:=REC2.PV_Out_ST31;
REC2_CNT:=0;
Rcv2MonErr:=FALSE;
END_IF; //A7d4//
 
IF (((NOT((NOT(Rcv1Err)) AND Rcv1NewData)) OR (((RdSysStEnOut) AND RedCPUOut) AND (NOT(Rcv1Run)))) OR
((NOT((NOT(Rcv2Err)) AND Rcv2NewData)) OR (((RdSysStEnOut) AND RedCPUOut) AND (NOT(Rcv2Run))))) THEN //A7d5//
IF (RcvMonCyc>0) THEN //A7d6//
IF ((REC1_CNT<RcvMonCyc) OR (REC2_CNT<RcvMonCyc)) THEN //A7d7//
IF (REC1_CNT<RcvMonCyc) THEN //A7d8//
Rcv1MonErr:=FALSE;
REC1_CNT:=REC1_CNT+1;
ELSE //A7d8//
Rcv1MonErr:=TRUE;
END_IF; //A7d9//
IF (REC2_CNT<RcvMonCyc) THEN //A7da//
Rcv2MonErr:=FALSE;
REC2_CNT:=REC2_CNT+1;
ELSE //A7da//
Rcv2MonErr:=TRUE;
END_IF;
ELSE //A7d7//
Rcv1MonErr:=TRUE;
Rcv2MonErr:=TRUE;
Rcv1Run:=FALSE;
Rcv1Mstr:=FALSE;
Rcv2Run:=FALSE;
Rcv2Mstr:=FALSE;
SyncLink:=FALSE;
ERR:=FALSE;
IF (SubOn) THEN //A7dd//
PV_Out0.Value:=SubsPV0;
PV_Out1.Value:=SubsPV1;
PV_Out2.Value:=SubsPV2;
PV_Out3.Value:=SubsPV3;
PV_Out4.Value:=SubsPV4;
PV_Out5.Value:=SubsPV5;
PV_Out6.Value:=SubsPV6;
PV_Out7.Value:=SubsPV7;
PV_Out8.Value:=SubsPV8;
PV_Out9.Value:=SubsPV9;
PV_Out10.Value:=SubsPV10;
PV_Out11.Value:=SubsPV11;
PV_Out12.Value:=SubsPV12;
PV_Out13.Value:=SubsPV13;
PV_Out14.Value:=SubsPV14;
PV_Out15.Value:=SubsPV15;
PV_Out16.Value:=SubsPV16;
PV_Out17.Value:=SubsPV17;
PV_Out18.Value:=SubsPV18;
PV_Out19.Value:=SubsPV19;
PV_Out20.Value:=SubsPV20;
PV_Out21.Value:=SubsPV21;
PV_Out22.Value:=SubsPV22;
PV_Out23.Value:=SubsPV23;
PV_Out24.Value:=SubsPV24;
PV_Out25.Value:=SubsPV25;
PV_Out26.Value:=SubsPV26;
PV_Out27.Value:=SubsPV27;
PV_Out28.Value:=SubsPV28;
PV_Out29.Value:=SubsPV29;
PV_Out30.Value:=SubsPV30;
PV_Out31.Value:=SubsPV31;
PV_Out0.ST:=B#16#60;
PV_Out1.ST:=B#16#60;
PV_Out2.ST:=B#16#60;
PV_Out3.ST:=B#16#60;
PV_Out4.ST:=B#16#60;
PV_Out5.ST:=B#16#60;
PV_Out6.ST:=B#16#60;
PV_Out7.ST:=B#16#60;
PV_Out8.ST:=B#16#60;
PV_Out9.ST:=B#16#60;
PV_Out10.ST:=B#16#60;
PV_Out11.ST:=B#16#60;
PV_Out12.ST:=B#16#60;
PV_Out13.ST:=B#16#60;
PV_Out14.ST:=B#16#60;
PV_Out15.ST:=B#16#60;
PV_Out16.ST:=B#16#60;
PV_Out17.ST:=B#16#60;
PV_Out18.ST:=B#16#60;
PV_Out19.ST:=B#16#60;
PV_Out20.ST:=B#16#60;
PV_Out21.ST:=B#16#60;
PV_Out22.ST:=B#16#60;
PV_Out23.ST:=B#16#60;
PV_Out24.ST:=B#16#60;
PV_Out25.ST:=B#16#60;
PV_Out26.ST:=B#16#60;
PV_Out27.ST:=B#16#60;
PV_Out28.ST:=B#16#60;
PV_Out29.ST:=B#16#60;
PV_Out30.ST:=B#16#60;
PV_Out31.ST:=B#16#60;
ELSE //A7dd//
PV_Out0.ST:=B#16#0;
PV_Out1.ST:=B#16#0;
PV_Out2.ST:=B#16#0;
PV_Out3.ST:=B#16#0;
PV_Out4.ST:=B#16#0;
PV_Out5.ST:=B#16#0;
PV_Out6.ST:=B#16#0;
PV_Out7.ST:=B#16#0;
PV_Out8.ST:=B#16#0;
PV_Out9.ST:=B#16#0;
PV_Out10.ST:=B#16#0;
PV_Out11.ST:=B#16#0;
PV_Out12.ST:=B#16#0;
PV_Out13.ST:=B#16#0;
PV_Out14.ST:=B#16#0;
PV_Out15.ST:=B#16#0;
PV_Out16.ST:=B#16#0;
PV_Out17.ST:=B#16#0;
PV_Out18.ST:=B#16#0;
PV_Out19.ST:=B#16#0;
PV_Out20.ST:=B#16#0;
PV_Out21.ST:=B#16#0;
PV_Out22.ST:=B#16#0;
PV_Out23.ST:=B#16#0;
PV_Out24.ST:=B#16#0;
PV_Out25.ST:=B#16#0;
PV_Out26.ST:=B#16#0;
PV_Out27.ST:=B#16#0;
PV_Out28.ST:=B#16#0;
PV_Out29.ST:=B#16#0;
PV_Out30.ST:=B#16#0;
PV_Out31.ST:=B#16#0;
END_IF;
END_IF; //A7de//
ELSE //A7d6//
Rcv1MonErr:=FALSE;
Rcv2MonErr:=FALSE;
END_IF;
END_IF; //A7d5//
 
IF ((((NOT(Rcv1Err)) AND Rcv1NewData) AND (((RdSysStEnOut) AND RedCPUOut) AND Rcv1Run)) OR
(((NOT(Rcv1Err)) AND Rcv1NewData) AND ((NOT(RdSysStEnOut)) OR (NOT(RedCPUOut))))) THEN //A7e0//
REC1_CNT:=0;
Rcv1MonErr:=FALSE;
END_IF; //A7e0//
IF ((((NOT(Rcv2Err)) AND Rcv2NewData) AND (((RdSysStEnOut) AND RedCPUOut) AND Rcv2Run)) OR
(((NOT(Rcv2Err)) AND Rcv2NewData) AND ((NOT(RdSysStEnOut)) OR (NOT(RedCPUOut))))) THEN //A7d1//
REC2_CNT:=0;
Rcv2MonErr:=FALSE;
END_IF; //A7d1//
END_IF;
 
END_FUNCTION_BLOCK




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Original library PCS7 IL (V9.0sp1) (zip, 20Mb)

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